The continuing demand for higher signal processing speeds and bandwidths in microminiaturized electronic circuit components has been accompanied by the application of semiconductor materials other than silicon to a variety of integrated circuit architectures. Currently foremost among the materials are III-V semiconductor compounds, particularly GaAs, which has a demonstrated ability to not only meet speed and bandwidth performance criteria, but inherently possesses a significant radiation hardness capability, thereby making GaAs-resident signal processing architectures especially attractive in aerospace environments.
Unfortunately, the performance advantage enjoyed by devices implemented in GaAs substrates is accompanied by a significant cost penalty due to the relatively low yield and poor predictability of electronic characteristics of GaAs chips. This lack of precision in GaAs chip processing methodologies also limits circuit integration density, so that a practical application of submicron processing techniques has not been effectively feasible in a GaAs environment.
Proposals to deal with these problems have been addressed in the literature and most recently have included self-aligned source/drain MESFET processes, as described, for example, in the U.S. Pat. No. 4,532,004 to Akiyama et al, and self-aligned substitutional gate MESFET processing, as described, for example, in the U.S. Pat. No. 4,569,119 to Terada et al..
In my copending U.S. Pat. No. 4,745,082, filed June 12, 1986, and issued May 17, 1988, entitled "Method of Making Self-Aligned MESFET Using a Substitutional Gate With Sidewalls" and assigned to the Assignee of the present application, there is described an improved substitutional gate MESFET processing methodology involving the formation of sidewall spacers contiguous with the substitutional gate (and self-aligned metal gate) to accurately control the channel length of the Schottky gate region and the performance characteristics of the device, while still maintaining the inherent self-aligned location of the gate metal in place of the "dummy" gate material. Now, although such an improved process results in a device having improved performance characteristics, the effective yield obtained remains diminished due to the potential for contamination of the surface of the GaAs substrate during processing steps subsequent to the formation of the `dummy` gate. Specifically, during the dry (reactive ion) etching of layers atop the surface of the GaAs substrate, the surface of the GaAs substrate is subjected to induced radiation damage by the ions in the plasma; in addition, the etching atmosphere contains contaminants (e.g. extremely light hydrogen ions and heavy metal ions such as Mg, Fe and Cr) that readily adhere to or penetrate the substrate surface, lodge themselves (form interstitial discontinuities) in the substrate and diffuse rapidly during subsequent high temperature annealing. Because these contaminants diffuse rapidly in GaAs and are electrically active, they can migrate into active device areas and spuriously compensate the electrical activation of the device, thereby reducing the yield of the wafer batch in which the chip containing the device is formed. Moreover, radiation damage to the GaAs surface may not be completely recoverable, further reducing the yield.